A NAND-type flash memory is widely used as a storage device for large-capacity data. Currently, cost reduction and increase in capacity per bit have progressed by miniaturizing a storage device, and further progress in miniaturization is required in the future. However, for further miniaturizing a flash memory, there are many problems to be solved such as suppression of a short channel effect, cell interferences, and variations between elements. Therefore, practical use of a novel storage device to replace a conventional floating gate-type flash memory is expected.
Recently, development of a two-terminal nonvolatile resistance change device represented by a ReRAM (Resistive Random Access Memory) has been actively carried out. This nonvolatile resistance change device is a promising candidate as a next-generation large-capacity storage device to replace the conventional floating gate-type flash memory in terms of a low-voltage operation, a high-speed switching, and a miniaturization capability. Specially, a memory in which amorphous silicon is used for a variable resistance layer attracts attention in terms of a high switching probability and the miniaturization capability.
The multi-level bit capability of a memory device increases storage density and functionality. As a technology for realizing multi-level bit capability of the above described two-terminal nonvolatile resistance change device, a method (current compliance control method) is employed in which the amount of current flowing into the nonvolatile resistance change device is controlled when changing from an off-state to an on-state.
In multi-level bit capability by such current compliance control method, reliability of the nonvolatile resistance change device is greatly affected, for example, by variation in resistance value due to an inflowing current from a parasitic capacitance of interconnection and a degree of expansion and contraction of a conductive filament. So, the current compliance control method may not be well-controlled filament formation and reduction.
Specially, the influence of the parasitic capacitance of interconnection on the reliability of a set operation (operation of transitioning from the off-state to the on-state) is large, so that it is pointed out that transistors need to be adjacent to each memory cell for performing an operation with a high reliability by the current compliance method.